1 6efd408f 2023-03-01 continue // uart_virt.cc
 2 6efd408f 2023-03-01 continue // QEMU `virt` generic virtual platform
 3 6efd408f 2023-03-01 continue 
 4 6efd408f 2023-03-01 continue 
 5 6efd408f 2023-03-01 continue #include <hw.h>
 6 6efd408f 2023-03-01 continue #include <uart.h>
 7 6efd408f 2023-03-01 continue #include <pl011.h>
 8 6efd408f 2023-03-01 continue 
 9 6efd408f 2023-03-01 continue 
10 6efd408f 2023-03-01 continue namespace Board {
11 6efd408f 2023-03-01 continue namespace Uart {
12 6efd408f 2023-03-01 continue 
13 6efd408f 2023-03-01 continue 
14 6efd408f 2023-03-01 continue namespace {
15 6efd408f 2023-03-01 continue 
16 3be3b31b 2023-03-02 continue constexpr uintptr_t UART_BASE = 0x9000000;
17 6efd408f 2023-03-01 continue 
18 6efd408f 2023-03-01 continue } // anonymous namespace
19 6efd408f 2023-03-01 continue 
20 6efd408f 2023-03-01 continue 
21 6efd408f 2023-03-01 continue void initialize()
22 6efd408f 2023-03-01 continue {
23 6efd408f 2023-03-01 continue     Pl011::ControlRegister ControlRegister;
24 6efd408f 2023-03-01 continue     ControlRegister.m_u.m_Bits.m_UartEnable = 1;
25 6efd408f 2023-03-01 continue     ControlRegister.m_u.m_Bits.m_TransmitEnable = 1;
26 621c3fa7 2023-03-02 continue     ControlRegister.m_u.m_Bits.m_ReceiveEnable = 1;
27 6efd408f 2023-03-01 continue     Hw::write32(UART_BASE + Pl011::CONTROL_REGISTER, ControlRegister.m_u.m_nValue);
28 6efd408f 2023-03-01 continue }
29 6efd408f 2023-03-01 continue 
30 6efd408f 2023-03-01 continue 
31 6efd408f 2023-03-01 continue void send(uint8_t nValue)
32 6efd408f 2023-03-01 continue {
33 6efd408f 2023-03-01 continue     // spin while fifo is full
34 6efd408f 2023-03-01 continue     for (; ; )
35 6efd408f 2023-03-01 continue     {
36 6efd408f 2023-03-01 continue         Pl011::FlagRegister FlagRegister{Hw::read32(UART_BASE + Pl011::FLAG_REGISTER)};
37 6efd408f 2023-03-01 continue         if (!FlagRegister.m_u.m_Bits.m_TransmitFifoFull)
38 6efd408f 2023-03-01 continue             break;
39 6efd408f 2023-03-01 continue     }
40 6efd408f 2023-03-01 continue     Hw::write32(UART_BASE + Pl011::DATA_REGISTER, nValue);
41 6efd408f 2023-03-01 continue }
42 6efd408f 2023-03-01 continue 
43 6efd408f 2023-03-01 continue 
44 6efd408f 2023-03-01 continue uint8_t recv()
45 6efd408f 2023-03-01 continue {
46 10d59256 2024-03-13 continue     // spin while fifo is full
47 621c3fa7 2023-03-02 continue     for (; ; )
48 621c3fa7 2023-03-02 continue     {
49 621c3fa7 2023-03-02 continue         Pl011::FlagRegister FlagRegister{Hw::read32(UART_BASE + Pl011::FLAG_REGISTER)};
50 621c3fa7 2023-03-02 continue         if (!FlagRegister.m_u.m_Bits.m_ReceiveFifoEmpty)
51 621c3fa7 2023-03-02 continue             break;
52 621c3fa7 2023-03-02 continue     }
53 621c3fa7 2023-03-02 continue     return Hw::read32(UART_BASE + Pl011::DATA_REGISTER) & 0xff;
54 6efd408f 2023-03-01 continue }
55 6efd408f 2023-03-01 continue 
56 6efd408f 2023-03-01 continue 
57 6efd408f 2023-03-01 continue } // namespace Uart
58 6efd408f 2023-03-01 continue } // namespace Board