1 6efd408f 2023-03-01 continue // uart_virt.cc
2 6efd408f 2023-03-01 continue // QEMU `virt` generic virtual platform
5 6efd408f 2023-03-01 continue #include <hw.h>
6 6efd408f 2023-03-01 continue #include <uart.h>
7 6efd408f 2023-03-01 continue #include <pl011.h>
10 6efd408f 2023-03-01 continue namespace Board {
11 6efd408f 2023-03-01 continue namespace Uart {
14 6efd408f 2023-03-01 continue namespace {
16 3be3b31b 2023-03-02 continue constexpr uintptr_t UART_BASE = 0x9000000;
18 6efd408f 2023-03-01 continue } // anonymous namespace
21 6efd408f 2023-03-01 continue void initialize()
23 6efd408f 2023-03-01 continue Pl011::ControlRegister ControlRegister;
24 6efd408f 2023-03-01 continue ControlRegister.m_u.m_Bits.m_UartEnable = 1;
25 6efd408f 2023-03-01 continue ControlRegister.m_u.m_Bits.m_TransmitEnable = 1;
26 621c3fa7 2023-03-02 continue ControlRegister.m_u.m_Bits.m_ReceiveEnable = 1;
27 6efd408f 2023-03-01 continue Hw::write32(UART_BASE + Pl011::CONTROL_REGISTER, ControlRegister.m_u.m_nValue);
31 6efd408f 2023-03-01 continue void send(uint8_t nValue)
33 6efd408f 2023-03-01 continue // spin while fifo is full
34 6efd408f 2023-03-01 continue for (; ; )
36 6efd408f 2023-03-01 continue Pl011::FlagRegister FlagRegister{Hw::read32(UART_BASE + Pl011::FLAG_REGISTER)};
37 6efd408f 2023-03-01 continue if (!FlagRegister.m_u.m_Bits.m_TransmitFifoFull)
40 6efd408f 2023-03-01 continue Hw::write32(UART_BASE + Pl011::DATA_REGISTER, nValue);
44 6efd408f 2023-03-01 continue uint8_t recv()
46 10d59256 2024-03-13 continue // spin while fifo is full
47 621c3fa7 2023-03-02 continue for (; ; )
49 621c3fa7 2023-03-02 continue Pl011::FlagRegister FlagRegister{Hw::read32(UART_BASE + Pl011::FLAG_REGISTER)};
50 621c3fa7 2023-03-02 continue if (!FlagRegister.m_u.m_Bits.m_ReceiveFifoEmpty)
53 621c3fa7 2023-03-02 continue return Hw::read32(UART_BASE + Pl011::DATA_REGISTER) & 0xff;
57 6efd408f 2023-03-01 continue } // namespace Uart
58 6efd408f 2023-03-01 continue } // namespace Board