2 // QEMU `virt` generic virtual platform
16 constexpr uintptr_t UART_BASE = 0x9000000;
18 } // anonymous namespace
23 Pl011::ControlRegister ControlRegister;
24 ControlRegister.m_u.m_Bits.m_UartEnable = 1;
25 ControlRegister.m_u.m_Bits.m_TransmitEnable = 1;
26 ControlRegister.m_u.m_Bits.m_ReceiveEnable = 1;
27 Hw::write32(UART_BASE + Pl011::CONTROL_REGISTER, ControlRegister.m_u.m_nValue);
31 void send(uint8_t nValue)
33 // spin while fifo is full
36 Pl011::FlagRegister FlagRegister{Hw::read32(UART_BASE + Pl011::FLAG_REGISTER)};
37 if (!FlagRegister.m_u.m_Bits.m_TransmitFifoFull)
40 Hw::write32(UART_BASE + Pl011::DATA_REGISTER, nValue);
48 Pl011::FlagRegister FlagRegister{Hw::read32(UART_BASE + Pl011::FLAG_REGISTER)};
49 if (!FlagRegister.m_u.m_Bits.m_ReceiveFifoEmpty)
52 return Hw::read32(UART_BASE + Pl011::DATA_REGISTER) & 0xff;