commit 69da5ffe1eeea1c4e88eaa4bbc4ce4ab4e296c94
from: Aleksey Ryndin <continue@to.any-key.press>
date: Sat Mar 16 17:25:31 2024 UTC

Append UART 16550: Initialize FIFO Control Register

commit - 42dfc04af51c29c3853644328b33f070c0f46f0c
commit + 69da5ffe1eeea1c4e88eaa4bbc4ce4ab4e296c94
blob - eafe421c10a35b5ef633100ee47fcee4c7b02880
blob + e12fb16f4c3017b5c462c6b4c4b43279565a4098
--- include/uart16550.h
+++ include/uart16550.h
@@ -8,13 +8,6 @@
 namespace Uart16550 {
 
 
-enum Register {
-    INTERRUPT_ENABLE_REGISTER   = 0x04,
-    MODEM_CONTROL_REGISTER      = 0x10,
-    LINE_STATUS_REGISTER        = 0x14,
-};
-
-
 struct InterruptEnableRegister {
     union _U {
         struct _Bits {
@@ -32,10 +25,35 @@ struct InterruptEnableRegister {
     {
         m_u.m_nValue = nValue;
     }
+
+    static constexpr auto OFFSET = 0x04;
 };
 static_assert(sizeof(InterruptEnableRegister) == 1, "should be byte");
 
 
+struct FifoControlRegister {
+    union _U {
+        struct _Bits {
+            uint8_t m_EnableFifos       : 1;
+            uint8_t m_RcvrFifoReset     : 1;
+            uint8_t m_XmitFifoReset     : 1;
+            uint8_t m_DmaMode           : 1;
+            uint8_t m_TxEmptyTrigger    : 2;
+            uint8_t m_RcvrTrigger       : 2;
+        } m_Bits;
+        uint8_t m_nValue;
+    } m_u;
+
+    explicit FifoControlRegister(uint8_t nValue = 0)
+    {
+        m_u.m_nValue = nValue;
+    }
+
+    static constexpr auto OFFSET = 0x08;
+};
+static_assert(sizeof(FifoControlRegister) == 1, "should be byte");
+
+
 struct ModemControlRegister {
     union _U {
         struct _Bits {
@@ -53,6 +71,8 @@ struct ModemControlRegister {
     {
         m_u.m_nValue = nValue;
     }
+
+    static constexpr auto OFFSET = 0x10;
 };
 static_assert(sizeof(ModemControlRegister) == 1, "should be byte");
 
@@ -76,6 +96,8 @@ struct LineStatusRegister {
     {
         m_u.m_nValue = nValue;
     }
+
+    static constexpr auto OFFSET = 0x14;
 };
 static_assert(sizeof(LineStatusRegister) == 1, "should be byte");
 
blob - c1fd4791e78f489855b40d6ee017d9fd57b40a3f
blob + 2e8d89e89f1d6851336fc4fe2137e6450fdac72c
--- uart_a64.cc
+++ uart_a64.cc
@@ -22,6 +22,21 @@ constexpr auto CLOCK_DIVISOR = (SERIAL_CLOCK + (BAUDRA
 
 static_assert(CLOCK_DIVISOR == 13, "Should be 13");
 
+
+template <typename T>
+T read()
+{
+    return T{Hw::read8(UART0_BASE + T::OFFSET)};
+}
+
+
+template <typename T>
+void write(T Register)
+{
+    Hw::write8(UART0_BASE + T::OFFSET, Register.m_u.m_nValue);
+}
+
+
 } // anonymous namespace
 
 
@@ -29,20 +44,23 @@ void initialize()
 {
     for (; ; )
     {
-        const Uart16550::LineStatusRegister LineStatusRegister {
-            Hw::read8(UART0_BASE + Uart16550::LINE_STATUS_REGISTER)
-        };
+        const auto LineStatusRegister{read<Uart16550::LineStatusRegister>()};
         if (LineStatusRegister.m_u.m_Bits.m_TransmitterEmpty)
             break;
     }
 
-    const Uart16550::InterruptEnableRegister InterruptEnableRegister{};
-    Hw::write8(UART0_BASE + Uart16550::INTERRUPT_ENABLE_REGISTER, InterruptEnableRegister.m_u.m_nValue);
+    write(Uart16550::InterruptEnableRegister{});
 
     Uart16550::ModemControlRegister ModemControlRegister;
     ModemControlRegister.m_u.m_Bits.m_DataTerminalReady = 1;
     ModemControlRegister.m_u.m_Bits.m_RequestToSend = 1;
-    Hw::write8(UART0_BASE + Uart16550::MODEM_CONTROL_REGISTER, ModemControlRegister.m_u.m_nValue);
+    write(ModemControlRegister);
+
+    Uart16550::FifoControlRegister FifoControlRegister;
+    FifoControlRegister.m_u.m_Bits.m_EnableFifos = 1;
+    FifoControlRegister.m_u.m_Bits.m_RcvrFifoReset = 1;
+    FifoControlRegister.m_u.m_Bits.m_XmitFifoReset = 1;
+    write(FifoControlRegister);
 }