commit eaada30ed38db2f345669dd9a51aec754326b694
from: Aleksey Ryndin <continue@to.any-key.press>
date: Fri Oct 20 15:58:26 2023 UTC

Append capsule/squat/reports/0.0.2.gmi (WiP)

commit - d0b6ad16c6db0d0d47f081de34eb97db9eb84d66
commit + eaada30ed38db2f345669dd9a51aec754326b694
blob - 4e96ba7189e5c7caa0583c2395209fcfba2949a5
blob + 2a438b5dc9f1da13bfebba47a4bba79221a38534
--- capsule/squat/reports/0.0.2.gmi
+++ capsule/squat/reports/0.0.2.gmi
@@ -104,11 +104,69 @@ aarch64-linux-gnu-objdump -d spl/u-boot-spl | less
     isb
 ```
 
-Тут макрос set_vbar разворачивается в пустышку.
-
-А код инициализации CNTFRQ выполняется:
+Для EL3: 
+* макрос set_vbar разворачивается в пустышку;
+* инициализируется регистр SCR_EL3 взведением флагов NS, IRQ, FIQ и EA:
+=> https://developer.arm.com/documentation/ddi0500/j/System-Control/AArch64-register-descriptions/Secure-Configuration-Register
+> [0] NS  = 1: EL0 and EL1 are in Non-secure state, memory accesses from those exception levels cannot access Secure memory.
+> [1] IRQ = 1: Physical IRQ while executing at all exception levels are taken in EL3.
+> [2] FIQ = 1: Physical FIQ while executing at all exception levels are taken in EL3.
+> [3] EA  = 1: External Aborts and SError Interrupts while executing at all exception levels are taken in EL3.
+* конфигурируется CPTR_EL3:
+=> https://developer.arm.com/documentation/ddi0500/d/system-control/aarch64-register-descriptions/architectural-feature-trap-register--el3
+> [31] TCPAC = 0: Does not cause access to the CPACR_EL1 or CPTR_EL2 to be trapped.
+> [10] TFP   = 0: Does not cause any instruction to be trapped.This is the reset value if the Advanced SIMD and Floating-point Extension is not implemented.
+* выполняется код инициализации CNTFRQ:
 => https://developer.arm.com/documentation/ddi0601/2023-06/AArch64-Registers/CNTFRQ-EL0--Counter-timer-Frequency-Register
 > Bits [31:0]
 > Clock frequency. Indicates the system counter clock frequency, in Hz.
 
+Для EL2:
+* макрос set_vbar разворачивается в пустышку;
+* инициализируется регистр CPTR_EL2 (Architectural Feature Trap Register)
+=> https://developer.arm.com/documentation/ddi0595/2021-03/AArch64-Registers/CPTR-EL2--Architectural-Feature-Trap-Register--EL2-
 
+Для EL1:
+* макрос set_vbar разворачивается в пустышку;
+* инициализируется регистр CPACR_EL1 (Architectural Feature Access Control Register)
+=> https://developer.arm.com/documentation/102226/0001/Register-descriptions/AArch64-system-registers/CPACR-EL1--Architectural-Feature-Access-Control-Register--EL1?lang=en
+> FPEN [21:20] = 0b11: No instructions are trapped.
+
+Затем выполняется инструкция-барьер isb, которая сбрасывает все пред-выбранные процессором инструкции.
+
+После чего в кода присутствуют вызовы двух функций: apply_core_errata, а затем lowlevel_init. Функция apply_core_errata состоит заглушек. А lowlevel_init является упрощенным враппером для вызова C функции s_init:
+```
+    /*
+     * Setup a temporary stack. Global data is not available yet.
+     */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+    ldr w0, =CONFIG_SPL_STACK
+#else
+    ldr w0, =CONFIG_SYS_INIT_SP_ADDR
+#endif
+    bic sp, x0, #0xf    /* 16-byte alignment for ABI compliance */
+
+    /*
+     * Save the old LR(passed in x29) and the current LR to stack
+     */
+    stp x29, x30, [sp, #-16]!
+
+    /*
+     * Call the very early init function. This should do only the
+     * absolute bare minimum to get started. It should not:
+     *
+     * - set up DRAM
+     * - use global_data
+     * - clear BSS
+     * - try to start a console
+     *
+     * For boards with SPL this should be empty since SPL can do all of
+     * this init in the SPL board_init_f() function which is called
+     * immediately after this.
+     */
+    bl  s_init
+    ldp x29, x30, [sp]
+    ret
+```
+
+Код s_init и вызываемых функций можно найти в директории arch/arm/mach-sunxi/.